Synchronous SRAM chip, 36M bit density, 1M x 36 configuration, featuring a 0.45 ns maximum access time and 250 MHz maximum clock rate. This QDR, pipelined architecture component operates at 1.8 V typical supply voltage. Housed in a 165-pin FBGA package with a 1 mm pin pitch, it is designed for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1415JV18-250BZC technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
18bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
250MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
870mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
1
Number of Words
1M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Cypress CY7C1415JV18-250BZC Datasheet
Download the complete datasheet for Cypress CY7C1415JV18-250BZC to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.