Cypress
CY7C342B-30JXI
CPLD MAX® Family 2.5K Gates 128 Macro Cells 40MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC
PackagePLCC
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Technical Specifications
Cypress CY7C342B-30JXI technical specifications.
General
| Package/Case | PLCC |
Compliance
| RoHS | Compliant |
Datasheet
Cypress CY7C342B-30JXI Datasheet
Download the complete datasheet for Cypress CY7C342B-30JXI to view detailed technical specifications.
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