MPC8272
NXP
This errata document describes corrections to the MPC8272 PowerQUICC II Family Reference Manual
Application NoteNxp
Errata to the MPC8272 PowerQUICC II Family Reference Manual
This addendum provides corrections and updates to the MPC8272 PowerQUICC II Family Reference Manual, covering power modes, PCI bridge settings, and memory controller configurations.
Overview
This document contains errata and addenda for the MPC8272 PowerQUICC II Family Reference Manual, Revision 2. It provides critical corrections to register descriptions, timing requirements, and functional specifications for the PowerQUICC II processor family. Key updates include modified HID0 register bit descriptions for stop mode, clarified reset configuration timing (rstconf# assertion), and corrected configuration EEPROM offsets. The manual includes detailed revisions for the PCI bridge interface, such as discard timer calculations and I2O compliance settings. Additionally, it provides updated register settings for SDRAM page-based and bank-based interleaving, UPM address multiplexing tables, and corrected IDMA and SCC bit field descriptions for data buffer byte ordering.
Use Cases
- Correcting errors in the MPC8272 hardware reference manual
- Configuring SDRAM and UPM memory controllers
- Designing PCI bus interfaces for PowerQUICC II processors
- Calculating discard timer values for delayed PCI reads
- Implementing proper reset configuration timing
Topics
MPC8272
PowerQUICC II
NXP
Freescale
errata
PCI bridge
SDRAM controller
memory interleaving
UPM
CPM
processor version register
Referenced Parts
| MPC8272 | NXP | This errata document describes corrections to the MPC8272 PowerQUICC II Family Reference Manual |