Dual-core programmable system-on-chip MCU combines a 150 MHz Arm Cortex-M4F core with a 100 MHz Cortex-M0+ core. The device family integrates 256 KB application flash, 32 KB supervisory flash, 128 KB SRAM, programmable digital logic, dual 12-bit 2 Msps SAR ADCs, a 12-bit DAC, comparators, opamps, CAPSENSE, USB Full-Speed, CAN FD, and serial communication peripherals. It operates from 1.7 V to 3.6 V and supports low-power modes including 7 µA Deep Sleep with 64 KB SRAM retention. Package options include 80-pin TQFP, 64-pin E-TQFP, and 68-pin QFN with industrial and extended-industrial temperature ranges.
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| CPU architecture | Dual-core Arm Cortex-M4F and Cortex-M0+ |
| Cortex-M4F maximum frequency | 150MHz |
| Cortex-M0+ maximum frequency | 100MHz |
| Application flash memory | 256KB |
| Supervisory flash memory | 32KB |
| SRAM | 128KB |
| Supply voltage | 1.7 to 3.6V |
| Deep Sleep current with 64 KB SRAM retention | 7µA |
| Serial communication blocks | 6 configurable SCBs |
| SAR ADC resolution | 12bit |
| SAR ADC sample rate | 2Msps |
| DAC resolution | 12bit |
| Programmable GPIO | Up to 62 |
| QSPI throughput | Up to 320Mbps |
| CAN FD data rate | Up to 5Mbps |
| Segment LCD drive | Up to 61 segments and 8 commons |
| Timer/counter/PWM blocks | 12 TCPWMs |
| Operating ambient temperature | -40 to 85; extended industrial -40 to 105°C |
| Package moisture sensitivity level | MSL3 |
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