256Mbyte SDRAM DRAM Module, 168DIMM, featuring a 64-bit data bus width and 256M bit chip density. This unbuffered dual in-line memory module operates at a maximum clock rate of 133 MHz with a CAS latency of 2. The module utilizes TSOP packaged chips, organized as 32Mx64, with a typical operating supply voltage of 3.3V. Designed for socket mounting, it offers a non-lead-frame SMT basic package type with 168 pins.
PackageUDIMM
MountingSocket
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Technical Specifications
Microchip W3DG6435V7D2 technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | DIM |
| Package/Case | UDIMM |
| Package Description | Unbuffered Dual In Line Memory Module |
| Lead Shape | No Lead |
| Pin Count | 168 |
| PCB | 168 |
| Package Length (mm) | 133.48(Max) |
| Package Width (mm) | 2.54(Max) |
| Package Height (mm) | 30.48(Max) |
| Mounting | Socket |
| Main Category | DRAM Module |
| Total Density | 256Mbyte |
| Module Type | 168DIMM |
| Maximum Clock Rate | 133MHz |
| Chip Density | 256Mbit |
| Subcategory | SDRAM |
| Data Bus Width | 64bit |
| Number of Chip per Module | 8 |
| Organization | 32Mx64 |
| Chip Package Type | TSOP |
| Typical Operating Supply Voltage | 3.3V |
| Maximum Operating Current | 880mA |
| Min Operating Supply Voltage | 3V |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Chip Configuration | 32Mx8 |
| ECC Support | No |
| CAS Latency | 2 |
Compliance
| Cage Code | 60991 |
| EU RoHS | No |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Microchip W3DG6435V7D2 Datasheet
Download the complete datasheet for Microchip W3DG6435V7D2 to view detailed technical specifications.
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