DDR SDRAM module offering 512Mbyte total density and 64-bit data bus width. Features 184-pin UDIMM form factor with a 1.27mm pin pitch, designed for socket mounting. Operates at a maximum clock rate of 266 MHz with a 0.75 ns maximum access time. Utilizes 8 x 512M bit TSOP chips for a 64Mx64 organization. Standard operating voltage is 2.5V, with a temperature range of 0°C to 70°C.
PackageUDIMM
MountingSocket
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Technical Specifications
Microchip W3EG6464S265JD3 technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | DIM |
| Package/Case | UDIMM |
| Package Description | Unbuffered Dual In Line Memory Module |
| Lead Shape | No Lead |
| Pin Count | 184 |
| PCB | 184 |
| Package Length (mm) | 133.48(Max) |
| Package Width (mm) | 2.54(Max) |
| Package Height (mm) | 30.48(Max) |
| Pin Pitch (mm) | 1.27 |
| Mounting | Socket |
| Main Category | DRAM Module |
| Total Density | 512Mbyte |
| Module Type | 184DIMM |
| Maximum Access Time | 0.75ns |
| Maximum Clock Rate | 266MHz |
| Chip Density | 512Mbit |
| Subcategory | DDR SDRAM |
| Data Bus Width | 64bit |
| Number of Chip per Module | 8 |
| Organization | 64Mx64 |
| Chip Package Type | TSOP |
| Typical Operating Supply Voltage | 2.5V |
| Maximum Operating Current | 3840mA |
| Min Operating Supply Voltage | 2.3V |
| Max Operating Supply Voltage | 2.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Chip Configuration | 64Mx8 |
| ECC Support | No |
| CAS Latency | 2.5 |
Compliance
| Cage Code | 60991 |
| EU RoHS | No |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Microchip W3EG6464S265JD3 Datasheet
Download the complete datasheet for Microchip W3EG6464S265JD3 to view detailed technical specifications.
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