Low-power integrated multiprotocol processor combines a static 68000 core with communications and system-integration blocks. The device provides two full-duplex serial communications controllers supporting HDLC/SDLC, UART, BISYNC, transparent modes, and autobaud operation. It includes 1152 bytes of on-chip dual-port RAM, three timers including watchdog support, a periodic interrupt timer, four programmable chip-select lines, and an on-chip PLL for 32 kHz or 4 MHz crystal operation. The processor supports 8-bit or 16-bit M68000-family system buses and is described for low-profile 100 TQFP packaging in space- and height-constrained applications.
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| Processor core | Static 68000 |
| System bus width | 8 or 16bit |
| Address bus width | 20bit |
| Serial communications controllers | 2 full-duplex SCCs |
| Supported protocols | HDLC/SDLC, UART, BISYNC, transparent modes, autobaud |
| Dual-port RAM | 1152bytes |
| Timers | 3 including watchdog timer |
| Chip-select lines | 4 programmable |
| DMA channels | 4 SDMA and 1 general-purpose DMA |
| Clock input options | 32 kHz or 4 MHz crystal via on-chip PLL |
| Maximum system frequency | 25MHz |
| Operating temperature range | 0 to 70 or -40 to 85, suffix dependent°C |
| Supply voltage absolute maximum | -0.3 to +7.0V |
| Storage temperature range | -55 to +150°C |
| Package | Low-profile 100 TQFP |
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