ColdFire V2 integrated microprocessor combines a 32-bit processor core with on-chip memory, DMA, timers, serial interfaces, and system integration logic. The device supports up to 54 MHz operation and delivers 50 MIPS with a 4 Kbyte direct-mapped instruction cache and 8 Kbyte on-chip SRAM. Integrated peripherals include a DRAM controller, two DMA channels, two UART modules, dual 16-bit timers, an M-Bus interface compatible with I2C, JTAG, and debug support. The processor operates from a 3.3 V supply with 5 V tolerant I/O and is supplied in a 160-pin PQFP package.
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| Processor core | Version 2 ColdFire |
| Data bus width | 32bit |
| Maximum operating frequency | 54MHz |
| Performance | 50 at 54 MHzMIPS |
| Instruction cache | 4 direct-mappedKbyte |
| On-chip SRAM | 8Kbyte |
| DMA channels | 2 fully programmable |
| UART channels | 2 full-duplex |
| Timers | Dual 16-bit general-purpose multimode timers |
| External address bus | 28bit |
| Internal address bus | 32bit |
| Chip selects | 8 programmable |
| Operating voltage | 3.0 to 3.6V |
| I/O tolerance | 5 tolerant padsV |
| Operating ambient temperature | 0 to 70; -40 to 85 extended temperature device°C |
| Package | 160-pin PQFP |
| JTAG frequency | 10 maximumMHz |
| M-Bus compatibility | I2C-compatible |
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