Six-core digital signal processor integrates six StarCore SC3850 DSP subsystems operating at 1 GHz. The device includes per-core L1 instruction and data caches, configurable L2 cache or M2 memory, 3072 Kbytes of shared M3 memory, and a 96 Kbyte boot ROM. High-speed interfaces include Serial RapidIO, PCI Express, CPRI, SGMII, RGMII Ethernet, SPI, I2C, UART, GPIO, and IEEE 1149.6 JTAG. The security engine accelerates cryptographic functions for IPSec, IKE, SSL/TLS, 3GPP, and LTE workloads in a 783-ball FC-PBGA package measuring 29 mm by 29 mm.
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| DSP core architecture | StarCore SC3850 |
| DSP core count | 6 |
| DSP core clock frequency | 1GHz |
| L1 instruction cache per core | 32Kbyte |
| L1 data cache per core | 32Kbyte |
| L2 cache or M2 memory per core | 512Kbyte |
| Shared M3 memory | 3072Kbyte |
| Boot ROM | 96Kbyte |
| DDR controller count | 1 |
| DDR data rate | 1333MHz |
| DDR data bus width | 64/32bit |
| DDR memory supported | 2Gbyte |
| DMA channels | 32 unidirectional |
| SerDes PHY lanes | 10 |
| Serial RapidIO interfaces | 2, x1/x2/x4 up to 5 Gbaud |
| PCI Express interface | x1/x2/x4 up to 5 Gbaud |
| CPRI lanes | 6 up to 6.144 Gbaud |
| Gigabit Ethernet interfaces | 2 RGMII or SGMII |
| UART bit rate | 6.25Mbps |
| GPIO ports | Up to 32 |
| JTAG standard | IEEE 1149.6 |
| Package dimensions | 29 x 29mm |
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Reference manual for the NXP MSC8157E, a six-core StarCore SC3850 DSP optimized for broadband wireless access with hardware acceleration and integrated security.
