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74HC02N

74HC02N

Nexperia
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Description:

NOR Gate 4-Element 2-IN CMOS 14-Pin PDIP

Country of Origin:

Thailand

Introduction date:

Dec 1, 1990

Updated: 07-SEP-2024

See moreLogic Gates by Nexperia

CADsCAD Models

Online version: https://www.datasheets.com/part-details/74hc02n-nexperia-82231051

overviewOverview

Familiarize yourself with the fundamental general information, properties, and characteristics of the component, along with its compliance with industry standards and regulations.

LifeCycleinfo
crownPremium
EU RoHS
rohs yesYes
RoHS Version
2011/65/EU, 2015/863
ECCNinfo
EAR99
Automotive
noNo
Supplier Cage Codeinfo
H2HX9
HTSUSAinfo
8542390060
Schedule Binfo
8542390060
PPAP
noNo
AEC Qualified
noNo
Category Path
Semiconductor > Standard and Specialty Logic > Standard Logic > Logic Gates

pdfDatasheet

Get a comprehensive understanding of the electronic component by downloading its datasheet. This PDF document includes all the necessary details, such as product overview, features, specifications, ratings, diagrams, applications, and more.

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packagePackage

The package information for the component gives important details about the product's size, weight, and packaging. This helps engineers determine if the product meets their requirements and expectations.

Supplier Package
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Pin Count
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PCB
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Tabinfo
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Package Length (mm)info
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Package Width (mm)info
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Package Height (mm)info
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Package Diameter (mm)
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Mounting
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Package Outline
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parametricParametric

The parametric information displays vital features and performance metrics of the component, which helps engineers and supply chain managers to compare and choose the most appropriate electronic component for their applications and needs.

Product Line
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Maximum Supply Current
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Maximum Storage Temperature
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Typical Quiescent Current
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Maximum Quiescent Current
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Supplier Temperature Grade
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Input Type
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Absolute Propagation Delay Time
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Minimum High Level Input Voltage
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Maximum Input Leakage Current
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Maximum Low Level Output Voltage
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Maximum Low Level Input Voltage
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Minimum High Level Output Voltage
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Propagation Delay Test Condition
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Number of Output Enables per Element
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Maximum High Level Output Current
infolock
Maximum Low Level Output Current
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Minimum Storage Temperature
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Number of Selection Inputs per Element
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Maximum Propagation Delay Time @ Maximum CL
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Typical Supply Current
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Logic Family
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Logic Function
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Process Technology
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Number of Elements per Chip
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Number of Element Inputs
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Number of Element Outputs
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Output Type
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Minimum Operating Temperature
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Maximum Operating Temperature
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Minimum Operating Supply Voltage
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Typical Operating Supply Voltage
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Maximum Operating Supply Voltage
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CADsCAD Models

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