DDR SDRAM module with 512Mbyte total density, featuring a 200-pin SODIMM package for socket mounting. This module operates at a maximum clock rate of 400 MHz with a 64-bit data bus width, organized as 64Mx64. It utilizes 512M bit chips with a 64Mx8 chip configuration and offers a CAS latency of 3. The module operates within a supply voltage range of 2.3V to 2.7V and has a temperature range of 0°C to 85°C.
PackageSODIMM
MountingSocket
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Technical Specifications
Swissbit SDN06464S4B51MT-50ER technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | DIM |
| Package/Case | SODIMM |
| Package Description | Small Outline Dual In Line Memory Module |
| Lead Shape | No Lead |
| Pin Count | 200 |
| PCB | 200 |
| Package Length (mm) | 67.6 |
| Package Height (mm) | 27 |
| Pin Pitch (mm) | 0.6 |
| Mounting | Socket |
| Main Category | DRAM Module |
| Total Density | 512Mbyte |
| Module Type | 200SODIMM |
| Maximum Access Time | 0.7ns |
| Maximum Clock Rate | 400MHz |
| Chip Density | 512Mbit |
| Subcategory | DDR SDRAM |
| Data Bus Width | 64bit |
| Number of Chip per Module | 8 |
| Organization | 64Mx64 |
| Typical Operating Supply Voltage | 2.5V |
| Maximum Operating Current | 3600mA |
| Min Operating Supply Voltage | 2.3V |
| Max Operating Supply Voltage | 2.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Chip Configuration | 64Mx8 |
| ECC Support | No |
| Number of Ranks | Single |
| CAS Latency | 3 |
Compliance
| Cage Code | SV183 |
| EU RoHS | Yes |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| ECCN | 4A994.a |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Swissbit SDN06464S4B51MT-50ER Datasheet
Download the complete datasheet for Swissbit SDN06464S4B51MT-50ER to view detailed technical specifications.
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