升级为高级版
XCZU21DR-2FFVD1156E
描述: | FPGA Zynq® UltraScale Family 930300 Cells 16nm Technology 0.95V 1156-Pin FCBGA |
厂商: | Advanced Micro Devices, Inc. |
推出日期: | Jun 19, 2013 |
上次检查日期: 21 SEP 2023 | |
查看更多Field Programmable Gate Arrays - FPGAs 属于 Advanced Micro Devices, Inc. | |
概述
概述熟悉该组件的基本一般信息、属性和特征，以及其与行业标准和法规的符合情况。
lifeCycle
EURohs
是RoHSVersion
2011/65/EU, 2015/863
ECCN
5A002.a.4
autoMotive
不是SupplierCageCode
6Z9Z3
HTSUSA
8542390001
SCHDULEB
8542390000
分类路径
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
数据手册
数据手册通过下载该电子元件的数据手册来全面了解其。这个PDF文档包含了所有必要的细节，如产品概述、特性、规格、评级、图表、应用等等。
修订日期:
数据表预览
封装
封装组件的包装信息提供了有关产品尺寸、重量和包装的重要细节。这有助于工程师确定产品是否符合其要求和期望。
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Basic Package Type
Package Family Name
Supplier Package
Package Description
Lead Shape
Pin Count
PCB
Tab
Package Length (mm)
Package Width (mm)
Package Height (mm)
Seated Plane Height (mm)
Pin Pitch (mm)
Package Diameter (mm)
Package Weight (g)
Package Material
Mounting
Package Outline
Package Orientation
Package Orientation Marking Type
Jedec
Jedec info (PKG outline)
制造
制造制造信息指定了生产和组装该组件的技术要求和规格。这些信息对于制造商来说至关重要，以保持组件的质量和可靠性，并确保其与其他设备和组件兼容。
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MSL
Maximum Reflow Temperature (°C)
Reflow Solder Time (Sec)
Number of Reflow Cycle
Standard
Reflow Temp. Source
Maximum Wave Temperature (°C)
Wave Solder Time (Sec)
Lead Finish(Plating)
Under Plating Material
Terminal Base Material
参数
参数参数信息显示了该组件的重要特性和性能指标，这有助于工程师和供应链经理比较和选择最适合其应用和需求的电子组件。
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生产线
Tolerant Configuration Interface Voltage
Temperature Flag
Typical Supply Current
Maximum Power Dissipation
Copy Protection
Digital Control Impedance
Device Logic Gates
JTAG Support
Maximum Supply Current
Number of I/O Banks
Maximum Differential I/O Pairs
Maximum I/O Performance
Maximum Distributed RAM Bits
Minimum Storage Temperature
Number of Inter Dielectric Layers
Maximum Storage Temperature
Maximum DSP Block Frequency
Maximum MLAB Capacity
Device PCIe Hard IP Blocks
Number of Regional Clocks
Maximum LVDS Data Rate
Device Logic Units
Tradename
In-System Programmability
Maximum Internal Frequency
Supplier Temperature Grade
Reprogrammability Support
Mega Multiply Accumulates per second
I/O Voltage
Shift Registers
Number of Global Clocks
Family Name
Maximum Number of User I/Os
Number of Registers
RAM Bits
Device Logic Cells
Number of Look-up Table Input
Device System Gates
Ethernet MACs
Number of Multipliers
Minimum Operating Supply Voltage
Processor Blocks
Typical Operating Supply Voltage
Transceiver Blocks
Maximum Operating Supply Voltage
Transceiver Speed
Program Memory Type
Dedicated DSP
PCI Blocks
Device Number of DLLs/PLLs
Total Number of Block RAM
Maximum Propagation Delay Time
Giga Multiply Accumulates per Second
Maximum Number of SERDES Channels
Speed Grade
Differential I/O Standards Supported
Single-Ended I/O Standards Supported
External Memory Interface
Supported IP Core
Supported IP Core Manufacture
Minimum Operating Temperature
Maximum Operating Temperature
Programmability
Process Technology
替代型号
替代型号