High-performance automotive AI domain controller SoC for centralized multi‑sensor perception, fusion and path planning in L2+–L4 AD/ADAS. Features Ambarella’s CVflow 3.0 AI accelerator, 12× Arm Cortex‑A78AE CPUs plus three dual‑core lockstep Cortex‑R52 pairs, integrated HDR ISP, H.265/H.264 video encoding, hardware security module and support for 4D imaging radar; fabricated on Samsung automotive‑grade 5 nm.
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Technical Specifications
Ambarella CV3-AD685 technical specifications.
General
| Product type | Automotive AI domain controller SoC |
| Autonomy support level | L2+ to L4 |
| AI accelerator | CVflow 3.0; ~20× NN processing vs. prior CV2 family |
| CPU cores | 12× Arm Cortex‑A78AE |
| Safety CPUs | 3× dual‑core Cortex‑R52 lockstep pairs |
| Functional safety target | ASIL‑B (chip‑level) with ASIL‑D safety island |
| Process technology | 5nm |
| Foundry process | Samsung automotive‑grade 5 nm |
| Image processing | Integrated HDR ISP; dense stereo and optical flow engines |
| Video encoding | H.265 (HEVC) and H.264 |
| Sensor modalities | Cameras, 4D imaging radar; supports multi‑sensor fusion and path planning |
| Security features | Hardware Security Module (HSM), TRNG, OTP, asymmetric/symmetric crypto acceleration, secure storage, DRAM scrambling/virtualization |
Compliance
| RoHS | Manufacturer states RoHS initiative compliance for semiconductor products |
Datasheet
Ambarella CV3-AD685 Datasheet
Download the complete datasheet for Ambarella CV3-AD685 to view detailed technical specifications.
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