Synchronous SRAM chip, 36M bit density, featuring a 1M x 36 configuration. Offers a maximum access time of 0.45 ns and a maximum clock rate of 633 MHz with QDR architecture. This surface mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1 mm pin pitch. Operates at a typical supply voltage of 1.8V, with a range of 1.7V to 1.9V, and supports a 2-port, pipelined architecture.
Cypress CY7C1265XV18-633BZXC technical specifications.
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