Synchronous SRAM chip, 18M-bit density, featuring a 512K x 36 configuration. Offers a maximum access time of 6.5 ns and a maximum clock rate of 133 MHz with SDR data rate architecture. This surface-mount component utilizes a 100-pin TQFP package with a 0.65mm pin pitch, operating at 3.3V. Designed with a flow-through architecture and four ports, it supports an 19-bit address bus.
Cypress CY7C1371DV33-133AXI technical specifications.
Download the complete datasheet for Cypress CY7C1371DV33-133AXI to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.