Synchronous SRAM chip, 18M-bit density, featuring a 512K x 36 configuration. Offers a maximum access time of 6.5 ns and a maximum clock rate of 133 MHz with SDR data rate architecture. This surface-mount component utilizes a 100-pin TQFP package with a 0.65mm pin pitch, operating at 3.3V. Designed with a flow-through architecture and four ports, it supports an 19-bit address bus.
PackageTQFP
MountingSurface Mount
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Technical Specifications
Cypress CY7C1371DV33-133AXI technical specifications.
General
Basic Package Type
Lead-Frame SMT
Package Family Name
QFP
Package/Case
TQFP
Package Description
Thin Quad Flat Package
Lead Shape
Gull-wing
Pin Count
100
PCB
100
Package Length (mm)
20
Package Width (mm)
14
Package Height (mm)
1.4
Seated Plane Height (mm)
1.6(Max)
Pin Pitch (mm)
0.65
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-026BHA
Density
18Mbit
Address Bus Width
19bit
Maximum Access Time
6.5ns
Timing Type
Synchronous
Maximum Clock Rate
133MHz
Data Rate Architecture
SDR
Density in Bits
18874368bit
Maximum Operating Current
210mA
Typical Operating Supply Voltage
3.3V
Number of Bits per Word
36bit
Number of Ports
4
Number of Words
512K
Min Operating Supply Voltage
3.135V
Max Operating Supply Voltage
3.6V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Flow-Through
Compliance
Cage Code
65786
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.b
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1371DV33-133AXI Datasheet
Download the complete datasheet for Cypress CY7C1371DV33-133AXI to view detailed technical specifications.
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