Synchronous SRAM chip, 36M-bit density, organized as 4M x 8 bits. Features a 0.45ns maximum access time and operates at a maximum clock rate of 200MHz with QDR architecture. This surface-mount component is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package measuring 17mm x 15mm x 0.89mm. It requires a typical operating supply voltage of 1.8V, with a range of 1.7V to 1.9V, and supports a 20-bit address bus.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1411JV18-200BZC technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
20bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
200MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
620mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
8bit
Number of Ports
1
Number of Words
4M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Cypress CY7C1411JV18-200BZC Datasheet
Download the complete datasheet for Cypress CY7C1411JV18-200BZC to view detailed technical specifications.
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