Synchronous SRAM chip, 144M-bit density, organized as 8M words by 18 bits. Features a 0.45 ns maximum access time and a 250 MHz maximum clock rate with DDR data rate architecture. Operates at 1.8 V typical supply voltage, with a 1.7 V to 1.9 V range. Housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package for surface mounting.
PackageFBGA
MountingSurface Mount
Quick Jump:
Technical Specifications
Cypress CY7C1623KV18-250BZXCT technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 165 |
| PCB | 165 |
| Package Length (mm) | 17 |
| Package Width (mm) | 15 |
| Package Height (mm) | 0.89 |
| Seated Plane Height (mm) | 1.4(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 144Mbit |
| Address Bus Width | 22bit |
| Maximum Access Time | 0.45ns |
| Timing Type | Synchronous |
| Maximum Clock Rate | 250MHz |
| Data Rate Architecture | DDR |
| Density in Bits | 150994944bit |
| Maximum Operating Current | 560mA |
| Typical Operating Supply Voltage | 1.8V |
| Number of Bits per Word | 18bit |
| Number of Ports | 2 |
| Number of Words | 8M |
| Min Operating Supply Voltage | 1.7V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Architecture | Pipelined |
Compliance
| Cage Code | 65786 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Cypress CY7C1623KV18-250BZXCT Datasheet
Download the complete datasheet for Cypress CY7C1623KV18-250BZXCT to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.