Synchronous SRAM chip, 72M-bit density, organized as 4M words x 18 bits. Features a 0.45ns maximum access time and operates at a maximum clock rate of 633MHz with DDR data rate architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch. It requires a typical operating supply voltage of 1.8V and supports a pipelined architecture.
Cypress CY7C2568XV18-633BZXCT technical specifications.
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