1M-bit Parallel NOR Flash memory, featuring a 128K x 8 organization and 70ns maximum access time. This integrated circuit operates from a 3V/3.3V supply and supports a 2.7 to 3.6V programming voltage. The device is housed in a 32-pin PLCC package with J-lead configuration for surface mounting. It includes a bottom boot block and an asynchronous timing interface.
PackagePLCC
MountingSurface Mount
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Technical Specifications
Cypress MBM29LV001BC-70PD technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | LCC |
| Package/Case | PLCC |
| Package Description | Plastic Leaded Chip Carrier |
| Lead Shape | J-Lead |
| Pin Count | 32 |
| PCB | 32 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Mbit |
| Interface Type | Parallel |
| Maximum Operating Current | 30mA |
| Block Organization | Asymmetrical |
| Architecture | Sectored |
| Programming Voltage | 2.7 to 3.6V |
| Timing Type | Asynchronous |
| Maximum Access Time | 70ns |
| Number of Words | 128K |
| Boot Block | Yes |
| Typical Operating Supply Voltage | 3|3.3V |
| Address Bus Width | 17bit |
| Location of Boot Block | Bottom |
| Number of Bits per Word | 8bit |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 65786 |
| EU RoHS | No |
| HTS Code | 8542320071 |
| Schedule B | 8542320070 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Cypress MBM29LV001BC-70PD Datasheet
Download the complete datasheet for Cypress MBM29LV001BC-70PD to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.