Dual J-K Flip-Flop IC, featuring negative edge triggering and complementary outputs. Operates with a supply voltage range of 2V to 3.6V, with a nominal 2.5V. 5V tolerant inputs enhance design flexibility. Industrial temperature grade (-40°C to 85°C) ensures reliable performance. Package is a 16-pin SOP (R-PDSO-G16) with a width of 5.3mm. Propagation delay is 9ns maximum.
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Technical Specifications
Fairchild 74LCX112SJ technical specifications.
General
| Max Operating Temperature | 85 |
| Number of Terminals | 16 |
| Min Operating Temperature | -40 |
| Terminal Position | DUAL |
| JEDEC Package Code | R-PDSO-G16 |
| Width | 5.3 |
| Length | 10.2 |
| Pin Count | 16 |
| Number of Functions | 2 |
| Temperature Grade | INDUSTRIAL |
| Supply Voltage-Nom (Vsup) | 2.5 |
| Supply Voltage-Max (Vsup) | 3.6 |
| Supply Voltage-Min (Vsup) | 2 |
| Logic IC Type | J-K FLIP-FLOP |
| Family | LVC/LCX/Z |
| Propagation Delay (tpd) | 9 |
| Number of Bits | 2 |
| Max I(ol) | 0.024 |
| Prop. Delay@Nom-Sup | 7.5 |
| Load Capacitance | 50 |
| Output Polarity | COMPLEMENTARY |
| Trigger Type | NEGATIVE EDGE |
| fmax-Min | 150 |
| Max Frequency@Nom-Sup | 150000000 |
Compliance
| RoHS | Yes |
| Eccn Code | EAR99 |
| Lead Free | Yes |
| HTS Code | 8542.39.00.01 |
| REACH | Compliant |
| Military Spec | False |
Datasheet
Fairchild 74LCX112SJ Datasheet
Download the complete datasheet for Fairchild 74LCX112SJ to view detailed technical specifications.
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