Synchronous SRAM chip with 72M-bit density, organized as 8M words by 8 bits. Features a 0.45ns maximum access time and a 333MHz maximum clock rate, utilizing a QDR data rate architecture. This integrated circuit is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package for surface mounting, operating at a typical supply voltage of 1.8V.
PackageFBGA
MountingSurface Mount
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Technical Specifications
GSI GS8662DT07BD-333 technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.94(Max)
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
72Mbit
Address Bus Width
21bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
333MHz
Data Rate Architecture
QDR
Density in Bits
75497472bit
Maximum Operating Current
630mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
8bit
Number of Ports
2
Number of Words
8M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Architecture
Pipelined
Compliance
Cage Code
3BKC7
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.b
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
GSI GS8662DT07BD-333 Datasheet
Download the complete datasheet for GSI GS8662DT07BD-333 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.