Synchronous SRAM chip, 72M-bit density, featuring a dual-port architecture with 8M words x 8 bits per word. Achieves a maximum access time of 0.45 ns and a maximum clock rate of 333 MHz, utilizing a QDR data rate architecture. Operates at 1.8V with a voltage range of 1.7V to 1.9V. Packaged in a 165-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, with dimensions of 15mm x 13mm x 0.94mm.
GSI GS8662DT07BGD-333 technical specifications.
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