Synchronous SRAM chip, 72M-bit density, featuring a 4M x 18 configuration with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 300 MHz, utilizing a QDR data rate architecture. This surface-mount component is housed in a 165-pin FBGA package with a 1mm pin pitch, operating at 1.8V typical supply voltage.
PackageFBGA
MountingSurface Mount
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Technical Specifications
GSI GS8662DT19BD-300T technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.94(Max)
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
72Mbit
Address Bus Width
20bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
300MHz
Data Rate Architecture
QDR
Density in Bits
75497472bit
Maximum Operating Current
580mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
4M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Architecture
Pipelined
Compliance
Cage Code
3BKC7
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
GSI GS8662DT19BD-300T Datasheet
Download the complete datasheet for GSI GS8662DT19BD-300T to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.