Synchronous SRAM chip, 72M-bit density, featuring a 2M x 36 configuration. Operates at a maximum clock rate of 167 MHz with a 0.5 ns access time. This QDR architecture component supports a 1.8V typical operating supply voltage and is housed in a 165-pin FBGA package for surface mounting. Designed for high-speed data transfer with a pipelined architecture.
PackageFBGA
MountingSurface Mount
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Technical Specifications
GSI GS8672D36AGE-167 technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
1.04(Max)
Seated Plane Height (mm)
1.5(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
72Mbit
Address Bus Width
19bit
Maximum Access Time
0.5ns
Timing Type
Synchronous
Maximum Clock Rate
167MHz
Data Rate Architecture
QDR
Density in Bits
75497472bit
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
2M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
3BKC7
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
GSI GS8672D36AGE-167 Datasheet
Download the complete datasheet for GSI GS8672D36AGE-167 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.