Synchronous SRAM chip, 72M-bit density, featuring a 2M x 36 configuration with a 20-bit address bus. Operates at a maximum clock rate of 300 MHz with a 0.45 ns maximum access time. This dual-port memory utilizes QDR architecture and a pipelined design, powered by a typical 1.8V supply voltage. Packaged in a 165-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
GSI GS8672Q36E-300I technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 165 |
| PCB | 165 |
| Package Length (mm) | 17 |
| Package Width (mm) | 15 |
| Package Height (mm) | 1.04(Max) |
| Seated Plane Height (mm) | 1.5(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 72Mbit |
| Address Bus Width | 20bit |
| Maximum Access Time | 0.45ns |
| Timing Type | Synchronous |
| Maximum Clock Rate | 300MHz |
| Data Rate Architecture | QDR |
| Density in Bits | 75497472bit |
| Typical Operating Supply Voltage | 1.8V |
| Number of Bits per Word | 36bit |
| Number of Ports | 2 |
| Number of Words | 2M |
| Min Operating Supply Voltage | 1.7V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| Architecture | Pipelined |
Compliance
| Cage Code | 3BKC7 |
| EU RoHS | No |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
GSI GS8672Q36E-300I Datasheet
Download the complete datasheet for GSI GS8672Q36E-300I to view detailed technical specifications.
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