Lattice Semiconductor
ispPAC-CLK5312S-01T48C
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP Tray
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP Tray
PackageTQFP
Quick Jump:
Technical Specifications
Lattice Semiconductor ispPAC-CLK5312S-01T48C technical specifications.
General
| Type | Clock Generator |
| Number of Inputs | 2 |
| Number of Outputs | 12 |
| Input Signal Type | Single-Ended|Differential |
| Output Signal Type | Single-Ended |
| Input Logic Level | HSTL|LVCMOS|LVDS|LVPECL|LVTTL|SSTL |
| Output Logic Level | eHSTL|HSTL|LVCMOS|LVTTL|SSTL |
| Minimum Input Frequency | 8MHz |
| Maximum Input Frequency | 267MHz |
| Minimum Output Frequency | 2.5MHz |
| Maximum Output Frequency | 267MHz |
| Maximum Duty Cycle | 53% |
| Maximum Fall Time | 5ns |
| Maximum Rise Time | 5ns |
| Maximum Output Skew | 100ps |
| Spread Spectrum | Yes |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Pin Count | 48 |
| Package/Case | TQFP |
| Package Family Name | QFP |
Compliance
| RoHS | No |
| RoHS Version | 2011/65/EU, 2015/863 |
Datasheet
Lattice Semiconductor ispPAC-CLK5312S-01T48C Datasheet
Download the complete datasheet for Lattice Semiconductor ispPAC-CLK5312S-01T48C to view detailed technical specifications.
No datasheet is available for this part.