Async Single SRAM chip, 4M-bit density (512K x 8 words), featuring a 55ns maximum access time. Operates with a 5V supply voltage (4.5V to 5.5V range) and consumes a maximum of 60mA. Housed in a 32-pin PDIP W through-hole package with a 2.54mm pin pitch. Suitable for operation between 0°C and 70°C.
PackagePDIP W
MountingThrough Hole
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Technical Specifications
Lyontek LY625128PL-55LL technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | PDIP W |
| Package Description | Plastic Dual In Line Package Wide Body |
| Lead Shape | Through Hole |
| Pin Count | 32 |
| PCB | 32 |
| Package Length (mm) | 41.91 |
| Package Width (mm) | 13.84 |
| Package Height (mm) | 3.94 |
| Seated Plane Height (mm) | 4.45(Min) |
| Pin Pitch (mm) | 2.54 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Density | 4Mbit |
| Address Bus Width | 19bit |
| Maximum Access Time | 55ns |
| Timing Type | Asynchronous |
| Density in Bits | 4194304bit |
| Maximum Operating Current | 60mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 8bit |
| Number of Ports | 1 |
| Number of Words | 512K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Lyontek LY625128PL-55LL Datasheet
Download the complete datasheet for Lyontek LY625128PL-55LL to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.