2M-bit NOR Flash memory with a parallel interface, featuring 256K x 8 organization and 120ns maximum access time. This integrated circuit operates from a 4.5 to 5.5V programming voltage and a typical 5V supply. It is housed in a 32-pin PLCC (Plastic Leaded Chip Carrier) package with J-lead configuration, designed for surface mounting. The memory architecture is sectored and asymmetrical, with an 18-bit address bus and a top boot block.
PackagePLCC
MountingSurface Mount
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Technical Specifications
Micron M29F002T120XK1 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | LCC |
| Package/Case | PLCC |
| Package Description | Plastic Leaded Chip Carrier |
| Lead Shape | J-Lead |
| Pin Count | 32 |
| PCB | 32 |
| Package Length (mm) | 14.05(Max) |
| Package Width (mm) | 11.51(Max) |
| Package Height (mm) | 2.8(Min) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-016AE |
| Density | 2Mbit |
| Interface Type | Parallel |
| Maximum Operating Current | 20mA |
| Block Organization | Asymmetrical |
| Architecture | Sectored |
| Programming Voltage | 4.5 to 5.5V |
| Timing Type | Asynchronous |
| Maximum Access Time | 120ns |
| Number of Words | 256K |
| Boot Block | Yes |
| Typical Operating Supply Voltage | 5V |
| Address Bus Width | 18bit |
| Location of Boot Block | Top |
| Number of Bits per Word | 8bit |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | 6Y440 |
| HTS Code | 8542320071 |
| Schedule B | 8542320070 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Micron M29F002T120XK1 Datasheet
Download the complete datasheet for Micron M29F002T120XK1 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.