2M-bit NOR Flash memory with a parallel interface, featuring 256K words x 8 bits organization and a maximum access time of 55ns. This integrated circuit operates at a typical 3.3V supply voltage, with a programming voltage range of 2.7 to 3.6V. The component is housed in a 32-pin PLCC (Plastic Leaded Chip Carrier) package with J-lead configuration, designed for surface mounting. It offers asymmetrical, sectored architecture with a top boot block and an 18-bit address bus.
PackagePLCC
MountingSurface Mount
Quick Jump:
Technical Specifications
Micron M29W022BT55K1 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | LCC |
| Package/Case | PLCC |
| Package Description | Plastic Leaded Chip Carrier |
| Lead Shape | J-Lead |
| Pin Count | 32 |
| PCB | 32 |
| Package Length (mm) | 14.1(Max) |
| Package Width (mm) | 11.56(Max) |
| Package Height (mm) | 3.18(Max) |
| Seated Plane Height (mm) | 3.56(Max) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-016AE |
| Density | 2Mbit |
| Interface Type | Parallel |
| Maximum Operating Current | 10mA |
| Block Organization | Asymmetrical |
| Architecture | Sectored |
| Programming Voltage | 2.7 to 3.6V |
| Timing Type | Asynchronous |
| Maximum Access Time | 55ns |
| Number of Words | 256K |
| Boot Block | Yes |
| Typical Operating Supply Voltage | 3.3V |
| Address Bus Width | 18bit |
| Location of Boot Block | Top |
| Number of Bits per Word | 8bit |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | 6Y440 |
| EU RoHS | Yes |
| HTS Code | 8542320071 |
| Schedule B | 8542320070 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Micron M29W022BT55K1 Datasheet
Download the complete datasheet for Micron M29W022BT55K1 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.