32M-bit NOR Flash memory with a parallel interface, offering 2M words x 16 bits. Features a 120ns maximum access time and operates from a typical 1.8V supply. This surface-mount component utilizes a 48-pin Thin Fine Pitch Ball Grid Array (TFBGA) package with 0.8mm pin pitch. Includes a bottom boot block and supports asymmetrical, sectored architecture.
PackageTFBGA
MountingSurface Mount
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Technical Specifications
Micron M59DR032B120ZB1T technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | TFBGA |
| Package Description | Thin Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 48 |
| PCB | 48 |
| Package Length (mm) | 12 |
| Package Width (mm) | 7 |
| Package Height (mm) | 1(Max) |
| Seated Plane Height (mm) | 1(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 32Mbit |
| Interface Type | Parallel |
| Maximum Operating Current | 20mA |
| Block Organization | Asymmetrical |
| Architecture | Sectored |
| Programming Voltage | 1.65 to 2.2|11.4 to 12.6V |
| Timing Type | Asynchronous |
| Maximum Access Time | 120ns |
| Number of Words | 2M |
| Boot Block | Yes |
| Typical Operating Supply Voltage | 1.8V |
| Address Bus Width | 21bit |
| Location of Boot Block | Bottom |
| Number of Bits per Word | 16bit |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | 6Y440 |
| HTS Code | 8542320071 |
| Schedule B | 8542320070 |
| ECCN | 3A991.b.1.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Micron M59DR032B120ZB1T Datasheet
Download the complete datasheet for Micron M59DR032B120ZB1T to view detailed technical specifications.
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