DDR2 SDRAM memory chip, 512Mbit density, organized as 128Mx4 with a 4-bit data bus width. Features a maximum clock rate of 533 MHz and a 16-bit address bus. Housed in a 60-pin FBGA package with a 0.8mm pin pitch, designed for surface mounting. Operates at a typical supply voltage of 1.8V, with a temperature range of -40°C to 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Micron MT47H128M4JN-37EIT:FTR technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 60 |
| PCB | 60 |
| Package Length (mm) | 10 |
| Package Width (mm) | 8 |
| Package Height (mm) | 0.8 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 512Mbit |
| Type | DDR2 SDRAM |
| Organization | 128Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 533MHz |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 32M |
| Maximum Access Time | 0.5ns |
| Density in Bits | 536870912bit |
| Address Bus Width | 16bit |
| Maximum Operating Current | 145mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 6Y440 |
| EU RoHS | No |
| HTS Code | 8542320028 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Micron MT47H128M4JN-37EIT:FTR Datasheet
Download the complete datasheet for Micron MT47H128M4JN-37EIT:FTR to view detailed technical specifications.
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