DDR2 SDRAM memory chip with 4.5 Gbit density, organized as 64Mx72 for a 72-bit data bus. Features a maximum clock rate of 400 MHz and 8 internal banks with 8M words per bank. Operates at 1.8V typical supply voltage, with a 16-bit address bus and 0.6 ns maximum access time. Packaged in a 255-pin BGA with surface mount configuration, measuring 32.1mm x 25.1mm x 2.03mm.
PackageBGA
MountingSurface Mount
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Technical Specifications
Micross AS4DDR264M72PBGR-5/ET technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | BGA |
| Package Description | Plastic Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 255 |
| PCB | 255 |
| Package Length (mm) | 32.1(Max) |
| Package Width (mm) | 25.1(Max) |
| Package Height (mm) | 2.03(Max) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 4.5Gbit |
| Type | DDR2 SDRAM |
| Organization | 64Mx72 |
| Data Bus Width | 72bit |
| Maximum Clock Rate | 400MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 8M |
| Maximum Access Time | 0.6ns |
| Density in Bits | 4831838208bit |
| Address Bus Width | 16bit |
| Maximum Operating Current | 600mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 105°C |
Compliance
| Cage Code | 0LRZ0 |
| EU RoHS | Yes |
| HTS Code | 8542320036 |
| Schedule B | 8542320023 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Micross AS4DDR264M72PBGR-5/ET Datasheet
Download the complete datasheet for Micross AS4DDR264M72PBGR-5/ET to view detailed technical specifications.
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