Standard SRAM, 128KX8, 100ns, CMOS, 0.450 X 0.550 INCH, LCC-32
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Technical Specifications
Pyramid P4C1024-100LMB technical specifications.
General
| Max Operating Temperature | 125 |
| Number of Terminals | 32 |
| Min Operating Temperature | -55 |
| Terminal Position | QUAD |
| JEDEC Package Code | R-XQCC-N32 |
| Width | 11.43 |
| Length | 13.97 |
| Pin Count | 32 |
| Number of Functions | 1 |
| Temperature Grade | MILITARY |
| Supply Voltage-Nom (Vsup) | 5 |
| Supply Voltage-Max (Vsup) | 5.5 |
| Supply Voltage-Min (Vsup) | 4.5 |
| Number of Words | 131072 |
| Number of Words Code | 128000 |
| Memory IC Type | STANDARD SRAM |
| Parallel/Serial | PARALLEL |
| Access Time-Max | 100 |
| Screening Level | MIL-STD-883 Class B |
Compliance
| RoHS | No |
| Eccn Code | 3A001.A.2.C |
| Lead Free | No |
| HTS Code | 8542.32.00.41 |
| REACH | Compliant |
| Military Spec | True |
Datasheet
Pyramid P4C1024-100LMB Datasheet
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