Asynchronous SRAM chip, 64K bit density, organized as 8K words by 8 bits. Features a 25 ns maximum access time and operates from a 5 V supply voltage (4.5 V to 5.5 V). This 28-pin Ceramic Dual In-line Package (CDIP) component is designed for through-hole mounting with a 2.54 mm pin pitch. Extended operating temperature range from -55 °C to 125 °C.
PackageCDIP
MountingThrough Hole
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Technical Specifications
Pyramid P4C164-25DMLF technical specifications.
General
Basic Package Type
Through Hole
Package Family Name
DIP
Package/Case
CDIP
Package Description
Ceramic Dual In Line Package
Lead Shape
Through Hole
Pin Count
28
PCB
28
Package Length (mm)
37.72(Max)
Package Width (mm)
7.87(Max)
Package Height (mm)
4.19(Max)
Seated Plane Height (mm)
5.72(Max)
Pin Pitch (mm)
2.54
Package Material
Ceramic
Mounting
Through Hole
Density
64Kbit
Address Bus Width
13bit
Maximum Access Time
25ns
Timing Type
Asynchronous
Density in Bits
65536bit
Maximum Operating Current
155mA
Typical Operating Supply Voltage
5V
Number of Bits per Word
8bit
Number of Ports
1
Number of Words
8K
Min Operating Supply Voltage
4.5V
Max Operating Supply Voltage
5.5V
Min Operating Temperature
-55°C
Max Operating Temperature
125°C
Compliance
Cage Code
3DTT2
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A001.a.2.c
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2002/95/EC
Datasheet
Pyramid P4C164-25DMLF Datasheet
Download the complete datasheet for Pyramid P4C164-25DMLF to view detailed technical specifications.
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