DDR2 SDRAM memory chip, 1Gbit density, organized as 256Mx4 with a 4-bit data bus width. Features a 667 MHz maximum clock rate and 8 internal banks. Housed in a 60-pin TFBGA package with a 0.8mm pin pitch, designed for surface mounting. Operates at 1.8V typical supply voltage, with a maximum access time of 0.45 ns and a temperature range of 0°C to 95°C.
PackageTFBGA
MountingSurface Mount
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Technical Specifications
Qimonda HYB18T1G400C2F-3S technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | TFBGA |
| Package Description | Thin Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 60 |
| PCB | 60 |
| Package Length (mm) | 12.5 |
| Package Width (mm) | 8 |
| Package Height (mm) | 1.02(Max) |
| Seated Plane Height (mm) | 1.2(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Gbit |
| Type | DDR2 SDRAM |
| Organization | 256Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 667MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 32M |
| Maximum Access Time | 0.45ns |
| Density in Bits | 1073741824bit |
| Address Bus Width | 17bit |
| Maximum Operating Current | 141mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 95°C |
Compliance
| EU RoHS | Yes |
| ECCN | EAR99 |
| RoHS Versions | 2002/95/EC |
Datasheet
Qimonda HYB18T1G400C2F-3S Datasheet
Download the complete datasheet for Qimonda HYB18T1G400C2F-3S to view detailed technical specifications.
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