Single-channel Ethernet PHY supporting 10/100 Mbps data rates, compliant with IEEE 802.3 and 802.3u standards. Features a 32-pin QFN package with surface-mount capability, measuring 5x5x0.95mm. Operates with a typical 3.3V analog power supply, within a 0°C to 70°C temperature range. Includes integrated Clock Data Recovery (CDR) for robust signal integrity.
PackageQFN
MountingSurface Mount
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Technical Specifications
Renesas 1894K-32LF technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | QFN |
| Package/Case | QFN |
| Package Description | Quad Flat No Lead Package |
| Lead Shape | No Lead |
| Pin Count | 32 |
| PCB | 32 |
| Package Length (mm) | 5 |
| Package Width (mm) | 5 |
| Package Height (mm) | 0.95(Max) |
| Seated Plane Height (mm) | 1(Max) |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Number of Channels per Chip | 1 |
| Maximum Data Rate | 100Mbps |
| PHY Line Side Interface | No |
| JTAG Support | No |
| Standard Supported | 10BASE-T|100BASE-T|100BASE-TX|IEEE 802.3|IEEE 802.3u |
| Typical Data Rate | 10/100Mbps |
| Integrated CDR | Yes |
| Power Supply Type | Analog |
| Min Operating Supply Voltage | 3.14V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Overhead Octet Support | No |
| Max Operating Supply Voltage | 3.47V |
| Typical Operating Supply Voltage | 3.3V |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Renesas 1894K-32LF Datasheet
Download the complete datasheet for Renesas 1894K-32LF to view detailed technical specifications.
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