128K-bit asynchronous SRAM chip featuring 8K x 16 organization and a 20ns maximum access time. This dual-port memory operates at 5V with a 4.5V to 5.5V supply range and supports SDR data rate architecture. Packaged in an 84-pin FPAK (Flat Package) with a 1.27mm pin pitch, it is designed for surface mounting. Operating across a -55°C to 125°C temperature range, this lead-frame SMT component offers a density of 131072 bits.
PackageFPAK
MountingSurface Mount
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Technical Specifications
Renesas 7025L20FGB8 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | FPAK |
| Package/Case | FPAK |
| Package Description | Flat Package |
| Lead Shape | Flat |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 29.72(Max) |
| Package Width (mm) | 29.72(Max) |
| Package Height (mm) | 2.67(Max) |
| Seated Plane Height (mm) | 3.56(Max) |
| Pin Pitch (mm) | 1.27 |
| Mounting | Surface Mount |
| Density | 128Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 20ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 131072bit |
| Maximum Operating Current | 320mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 16bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 7025L20FGB8 Datasheet
Download the complete datasheet for Renesas 7025L20FGB8 to view detailed technical specifications.
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