Asynchronous SRAM chip offering 128K bit density, organized as 8K words by 16 bits. Features a maximum access time of 15 ns and operates with a typical supply voltage of 5V. This dual-port memory utilizes SDR architecture and is housed in an 84-pin FPAK lead-frame SMT package with a 1.27mm pin pitch. Designed for surface mounting, it supports an address bus width of 26 bits and operates within a temperature range of 0°C to 70°C.
PackageFPAK
MountingSurface Mount
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Technical Specifications
Renesas 7025S15FG8 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | FPAK |
| Package/Case | FPAK |
| Package Description | Flat Package |
| Lead Shape | Flat |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 29.72(Max) |
| Package Width (mm) | 29.72(Max) |
| Package Height (mm) | 2.67(Max) |
| Seated Plane Height (mm) | 3.56(Max) |
| Pin Pitch (mm) | 1.27 |
| Mounting | Surface Mount |
| Density | 128Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 15ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 131072bit |
| Maximum Operating Current | 310mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 16bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 7025S15FG8 Datasheet
Download the complete datasheet for Renesas 7025S15FG8 to view detailed technical specifications.
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