Asynchronous SRAM chip with 128K bit density, organized as 8K words by 16 bits. Features a 55ns maximum access time and dual port architecture. Operates at a typical 5V supply voltage, with a range of 4.5V to 5.5V. Housed in an 84-pin Ceramic Pin Grid Array (CPGA) package for through-hole mounting.
PackageCPGA
MountingThrough Hole
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Technical Specifications
Renesas 7025S55GG8 technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | PGA |
| Package/Case | CPGA |
| Package Description | Ceramic Pin Grid Array |
| Lead Shape | Through Hole |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 28.45(Max) |
| Package Width (mm) | 28.45(Max) |
| Package Height (mm) | 3.68(Max) |
| Seated Plane Height (mm) | 5.21(Max) |
| Pin Pitch (mm) | 2.54 |
| Package Material | Ceramic |
| Mounting | Through Hole |
| Density | 128Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 55ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 131072bit |
| Maximum Operating Current | 250mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 16bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 7025S55GG8 Datasheet
Download the complete datasheet for Renesas 7025S55GG8 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.