64K-bit asynchronous SRAM chip featuring 8K x 8 organization and 20ns maximum access time. This surface-mount component utilizes a 64-pin Thin Quad Flat Package (TQFP) with a 0.8mm pin pitch. It operates with a 3.3V supply voltage and supports a 26-bit address bus. The dual-port architecture and SDR data rate make it suitable for various embedded applications.
PackageTQFP
MountingSurface Mount
Quick Jump:
Technical Specifications
Renesas 70V05S20PFI8 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | TQFP |
| Package Description | Thin Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 64 |
| PCB | 64 |
| Package Length (mm) | 14 |
| Package Width (mm) | 14 |
| Package Height (mm) | 1.4 |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-026BEB |
| Density | 64Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 20ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 65536bit |
| Maximum Operating Current | 225mA |
| Typical Operating Supply Voltage | 3.3V |
| Number of Bits per Word | 8bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 3V |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | SAN34 |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 70V05S20PFI8 Datasheet
Download the complete datasheet for Renesas 70V05S20PFI8 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.