8735AK-21

Zero delay buffer, a clock generator, features a single differential input and a single differential LVPECL output. This surface-mount component operates with input and output frequencies ranging from 31.25 MHz to 700 MHz. It supports various input logic levels including HCSL, LVDS, LVHSTL, LVPECL, and SSTL. The device is housed in a 32-pin VFQFPN EP package with a 0.5mm pin pitch, measuring 5x5x0.85mm. Key performance specifications include a maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 20 ps.