LVPECL differential clock buffer and driver, featuring a single differential input and single differential output. This surface-mount integrated circuit operates with input and output frequencies from 31.25 MHz to 700 MHz. It offers a maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 20 ps. The component is housed in a 32-pin VFQFPN EP package with a 0.5 mm pin pitch, measuring 5x5x0.85 mm.
PackageVFQFPN EP
MountingSurface Mount
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Technical Specifications
Renesas 8735AK-21T technical specifications.
General
Basic Package Type
Non-Lead-Frame SMT
Package Family Name
QFN
Package/Case
VFQFPN EP
Package Description
Very Fine Quad Flat Package No Lead, Exposed Pad
Lead Shape
No Lead
Pin Count
32
PCB
32
Package Length (mm)
5
Package Width (mm)
5
Package Height (mm)
0.85(Max)
Seated Plane Height (mm)
0.9(Max)
Pin Pitch (mm)
0.5
Package Material
Plastic
Mounting
Surface Mount
Type
Clock Generator
Number of Inputs
1
Number of Outputs
1
Input Signal Type
Differential
Output Signal Type
Differential
Input Logic Level
HCSL|LVDS|LVHSTL|LVPECL|SSTL
Output Logic Level
LVPECL
Minimum Input Frequency
31.25MHz
Maximum Input Frequency
700MHz
Minimum Output Frequency
31.25MHz
Maximum Output Frequency
700MHz
Maximum Cycle to Cycle Jitter
25ps
Maximum Duty Cycle
53%
Maximum Fall Time
0.7ns
Maximum Rise Time
0.7ns
Maximum Output Skew
20ps
Spread Spectrum
No
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Compliance
Cage Code
SAN34
EU RoHS
No
HTS Code
8542390001
Schedule B
8542390000
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Renesas 8735AK-21T Datasheet
Download the complete datasheet for Renesas 8735AK-21T to view detailed technical specifications.
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