Dual negative edge-triggered J-K flip-flop with complementary outputs. This CMOS logic IC operates with a minimum supply voltage of 3V and a maximum of 3.6V, featuring a nominal supply of 3.3V. It supports a maximum clock frequency of 125MHz and a propagation delay of 15ns. The device is housed in a 16-lead small outline package (SOP) with gull wing terminals, measuring 9.9mm in length, 3.95mm in width, and a maximum seated height of 1.75mm. Operating within an industrial temperature range of -40°C to 85°C, this surface-mount component offers two flip-flop functions.
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Technical Specifications
Renesas HD74AC112RP technical specifications.
General
| Clock Edge Trigger Type | Negative Edge |
| fmax-Min | 125MHz |
| Height - Seated (Max) | 1.75mm |
| JESD-30 Code | R-PDSO-G16 |
| JESD-609 Code | e0 |
| Length | 9.9mm |
| Logic IC Type | J-K FLIP-FLOP |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | Complementary |
| Package Body Material | Plastic |
| Package Code | SOP |
| Package Shape | Rectangular |
| Package Style | SMALL OUTLINEMeter |
| Propagation Delay (tpd) | 15ns |
| Qualification Status | Not Qualified |
| Reach SVHC Compliant | Yes |
| RoHS Compliant | No |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 3V |
| Supply Voltage-Nom (Vsup) | 3.3V |
| Surface Mount | Yes |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Tin |
| Terminal Form | Gull Wing |
| Terminal Pitch | 1.27mm |
| Terminal Position | DUAL |
| Width | 3.95mm |
Compliance
| RoHS | Not Compliant |
Datasheet
Renesas HD74AC112RP Datasheet
Download the complete datasheet for Renesas HD74AC112RP to view detailed technical specifications.
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