Dual J-K flip-flop IC with complementary outputs, operating on a 2V to 6V supply range. Features negative edge triggering for clock input and a maximum operating frequency of 24MHz. CMOS technology ensures low power consumption. Packaged in a 14-pin plastic dual in-line package (PDIP) with through-hole mounting and a 2.54mm terminal pitch. Maximum propagation delay is 190ns.
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Technical Specifications
Renesas HD74HC107P technical specifications.
General
| Clock Edge Trigger Type | Negative Edge |
| Height - Seated (Max) | 5.06mm |
| JESD-30 Code | R-PDIP-T14 |
| JESD-609 Code | e0 |
| Length | 19.2mm |
| Load Capacitance | 50pF |
| Logic IC Type | J-K FLIP-FLOP |
| Max Frequency@Nom-Sup | 24MHz |
| Max I(ol) | 4A |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | Complementary |
| Package Body Material | Plastic |
| Package Code | DIP |
| Package Equivalence Code | DIP14,.3 |
| Package Shape | Rectangular |
| Package Style | IN-LINEMeter |
| Power Supplies | 2/6V |
| Propagation Delay (tpd) | 190ns |
| Qualification Status | Not Qualified |
| RoHS Compliant | No |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Supply Voltage-Nom (Vsup) | 4.5V |
| Surface Mount | No |
| Technology | CMOS |
| Temperature Grade | INDUSTRIAL |
| Terminal Finish | Tin |
| Terminal Form | Through Hole |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Width | 7.62mm |
Compliance
| RoHS | Not Compliant |
Datasheet
Renesas HD74HC107P Datasheet
Download the complete datasheet for Renesas HD74HC107P to view detailed technical specifications.
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