16-bit CISC microcontroller featuring an M16C/60 core, operating at up to 24 MHz. This surface-mount device offers 96KB of ROM program memory and 5KB of RAM. It includes 87 programmable I/Os, 11 timers, 3 UART interfaces, and 26 ADC channels with 8-bit DAC capabilities. Packaged in a 100-pin PQFP (Plastic Quad Flat Package) with gull-wing leads, measuring 20mm x 14mm x 2.8mm, it supports a maximum operating supply voltage of 5.5V.
PackagePQFP
MountingSurface Mount
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Technical Specifications
Renesas M30622MAP-110FP technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | PQFP |
| Package Description | Plastic Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 100 |
| PCB | 100 |
| Package Length (mm) | 20 |
| Package Width (mm) | 14 |
| Package Height (mm) | 2.8 |
| Seated Plane Height (mm) | 3.05(Max) |
| Pin Pitch (mm) | 0.65 |
| Package Weight (g) | 1.6 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-112CC-1 |
| Family Name | M16C |
| Data Bus Width | 16bit |
| Instruction Set Architecture | CISC |
| Maximum Clock Rate | 24MHz |
| Maximum CPU Frequency | 24MHz |
| Device Core | M16C/60 |
| Program Memory Type | ROM |
| Program Memory Size | 96KB |
| RAM Size | 5KB |
| Number of Programmable I/Os | 87 |
| Programmability | Yes |
| Number of Timers | 11 |
| Interface Type | UART |
| CAN | 0 |
| I2C | 0 |
| SPI | 0 |
| Ethernet | 0 |
| UART | 3 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 5.5V |
| ADC Channels | 26 |
| Number of ADCs | Single |
| DAC Channels | 2 |
| DAC Resolution | 8bit |
| Number of DACs | Single |
Compliance
| Cage Code | SAN34 |
| EU RoHS | No |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | Yes |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Renesas M30622MAP-110FP Datasheet
Download the complete datasheet for Renesas M30622MAP-110FP to view detailed technical specifications.
No datasheet is available for this part.