Synchronous SRAM chip featuring 36M-bit density, organized as 2M x 18 bits, with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 250 MHz, utilizing a QDR data rate architecture. This dual-port memory operates at 1.8V and is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package suitable for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Renesas R1Q2A3618BBG-40RB technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
1.08
Seated Plane Height (mm)
1.4
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
20bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
250MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
650mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
2M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Compliance
Cage Code
SAN34
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Renesas R1Q2A3618BBG-40RB Datasheet
Download the complete datasheet for Renesas R1Q2A3618BBG-40RB to view detailed technical specifications.
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