Synchronous SRAM chip featuring 36M-bit density, organized as 2M x 18 bits, with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 250 MHz, utilizing a QDR data rate architecture. This dual-port memory operates at 1.8V and is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package suitable for surface mounting.
Renesas R1Q2A3618BBG-40RB technical specifications.
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