Synchronous SRAM chip, 36M-bit density, featuring a 1M x 36 configuration with a 19-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 200 MHz, utilizing a QDR data rate architecture. This dual-port memory operates at 1.8V, with a voltage range of 1.7V to 1.9V. Packaged in a 165-pin FBGA (Fine Pitch Ball Grid Array) with a 1mm pin pitch, suitable for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Renesas R1Q2A3636BBG-50RT technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
1.08
Seated Plane Height (mm)
1.4
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
19bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
200MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
650mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
1M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Compliance
Cage Code
SAN34
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Renesas R1Q2A3636BBG-50RT Datasheet
Download the complete datasheet for Renesas R1Q2A3636BBG-50RT to view detailed technical specifications.
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