This registered buffer IC features 13 input and 26 output elements, operating on a CMOS process technology. It is packaged in a 56-pin Very Fine Quad Flat Package No Lead, Exposed Pad (VFQFPN EP) with a seated plane height of 0.9mm. The IC is designed for surface mount applications and has a non-inverting polarity with positive-edge/negative-edge triggering.
PackageVFQFPN EP
MountingSurface Mount
PolarityNon-Inverting
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Technical Specifications
Renesas SSTVA16859CKLF technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | QFN |
| Package/Case | VFQFPN EP |
| Package Description | Very Fine Quad Flat Package No Lead, Exposed Pad |
| Lead Shape | No Lead |
| Pin Count | 56 |
| PCB | 56 |
| Package Length (mm) | 8 |
| Package Width (mm) | 8 |
| Package Height (mm) | 0.88 |
| Seated Plane Height (mm) | 0.9 |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Logic Family | SSTV |
| Logic Function | Registered Buffer |
| Process Technology | CMOS |
| Number of Elements per Chip | 1 |
| Number of Element Inputs | 13 |
| Number of Element Outputs | 26 |
| Polarity | Non-Inverting |
| Triggering Type | Positive-Edge/Negative-Edge |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Renesas SSTVA16859CKLF Datasheet
Download the complete datasheet for Renesas SSTVA16859CKLF to view detailed technical specifications.
No datasheet is available for this part.