512Mbit DDR SDRAM memory chip, organized as 128Mx4, featuring a 4-bit data bus width and a maximum clock rate of 333 MHz. This surface-mount component utilizes a 60-pin FBGA package with a 12mm x 9mm footprint and a maximum seated plane height of 1.2mm. Operating at a typical supply voltage of 2.5V, it offers 4 internal banks and a maximum access time of 0.7 ns.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Samsung K4H510438G-HCB3 technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 60 |
| PCB | 60 |
| Package Length (mm) | 12 |
| Package Width (mm) | 9 |
| Seated Plane Height (mm) | 1.2(Max) |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 512Mbit |
| Type | DDR SDRAM |
| Organization | 128Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 333MHz |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 32M |
| Maximum Access Time | 0.7ns |
| Density in Bits | 536870912bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 210mA |
| Typical Operating Supply Voltage | 2.5V |
| Max Operating Supply Voltage | 2.7V |
| Min Operating Supply Voltage | 2.3V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | 1542F |
| HTS Code | 8542320028 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Samsung K4H510438G-HCB3 Datasheet
Download the complete datasheet for Samsung K4H510438G-HCB3 to view detailed technical specifications.
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