GDDR3 SDRAM memory chip, 1Gbit density, organized as 32Mx32 with a 32-bit data bus width. Features a maximum clock rate of 2000 MHz and 8 internal banks. Packaged in a 136-pin FBGA (Fine Pitch Ball Grid Array) with surface mount capability. Operates at a typical supply voltage of 1.8V, with a 0°C to 85°C operating temperature range.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Samsung K4J10324KE-HC1A technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 136 |
| PCB | 136 |
| Package Length (mm) | 14 |
| Package Width (mm) | 10 |
| Seated Plane Height (mm) | 1.12 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Gbit |
| Type | GDDR3 SDRAM |
| Organization | 32Mx32 |
| Data Bus Width | 32bit |
| Maximum Clock Rate | 2000MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 4M |
| Maximum Access Time | 0.2ns |
| Density in Bits | 1073741824bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 620mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 1542F |
| HTS Code | 8542320032 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Samsung K4J10324KE-HC1A Datasheet
Download the complete datasheet for Samsung K4J10324KE-HC1A to view detailed technical specifications.
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